1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a cell array of point-symmetrically arranged SRAM (Static Random Access Memory) cells arrayed in a matrix.
2. Description of the Related Art
In general, an SRAM memory macro comprises an SRAM cell array having a plurality of SEAM cells arranged in a bit line and a word line direction in a matrix; and a peripheral circuit including a local sense amp, a row decoder, an I/O controller and other control circuits. In recent years, for the purpose of reducing parasitic capacities associated with bit lines to achieve fast access as the memory capacity increases, such an SRAM memory macro is known that includes multi-split SRAM cell arrays. In such the SRAM memory macro, local sense amps are each arranged between plural SRAM cell arrays aligned in the bit line direction, and an I/O controller is arranged at the end of series of the SRAM cell arrays. (Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, B. Zheng, and Mark Bohr, “SRAM Design on 65-nm CMOS Technology With Dynamic Sleep Transistor for Leakage Reduction”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, No. 4, APRIL 2005.)
Usually, an SRAM cell includes two sets of loads formed of P-channel MOS transistors, and two sets of drivers and transfers formed of N-channel MOS transistors, a total of 6 MOS transistors. The SRAM cell is laid out in a point-symmetric pattern within an N-well region and both-side P-well regions. More specifically, sources and drains of the transistors are aligned in parallel with a boundary line between well regions, and gates are arranged extending in a direction orthogonal to the boundary line (see U.S. Pat. No. 6,677,649, for example). The point-symmetric pattern is advantageous because a diffused layer is not L-shaped and the layout contains no uselessness. In accordance with the layout, P-well regions and N-well regions are patterned in stripes extending in the bit line direction and arranged alternately in the word line direction over the SRAM cell arrays.
In the local sense amps laid-out between the SRAM cell arrays and the I/O controller arranged at the end of a series of the SRAM cell arrays, P-well regions and N-well regions are shaped in stripes extending in parallel with the word line. If the SRAM cell arrays differ from the peripheral circuits in the arrangement direction of and the length of the well in this way, problems occur with respect to the following two points. First, it is required to interpose a process dummy SRAM cell between the SRAM cell array and the peripheral circuit. Second, variations in processing of wells become larger and deteriorate the characteristics of transistors.